A Synchronous Buck dc-dc Converter, high side P-type MOSFET
This circuit extends the earlier circuits, still making use of the simpler p-type MOSFET approach for the high-side switch, but adding an n-type MOSFET for the low side switch to form a synchronous converter. A microcontroller is used to provide the control electronics as suitable controller devices are not readily available. The low-side switch effectively bypasses the catch diode used in the earlier circuits and reduces the power loss due to that diode. This is effective only if the MOSFET voltage drop is much less than that of the diode.
The use of a microcontroller in these types of circuits introduces a number of difficult questions concerning transient response of the resulting circuit, which must cope with a significant delay between sampling of changes in the output voltage and response of the PWM signal. These questions will be addressed elsewhere, as will the appropriate choice of microprocessor.
The microcontroller used was one that was readily at hand and is certainly not the best choice for a final application. At the low powers we are using its high current drain completely kills the overall efficiency. However the purpose of this circuit is to allow us to test out a variety of control algorithms.
The microcontroller used is one of the 28 pin slimline DIP ATMega8 family, of which the ATMega48 has the smallest program memory capacity. The circuit uses techniques that have already been described earlier for the switching MOSFETs and their totem-pole drivers. The output voltage is divided down and passed back to the A/D converter multiplexer input 0. This is the only variable that is controlled with this circuit. The Schottky diode D1 is included to provide a path for the inductor current while the low side MOSFET switch Q6 is off, which must happen for a short period at the beginning and end of the switching duty cycle. A level shifter (Q7) is required as the microcontroller must operate at 5V. The header H1 is provided to allow in-circuit programming of the microcontroller via the SPI port. During a reset period, which can be quite long, particularly during programming, the control outputs PB1 and PB2 must be pulled low to ensure the two MOSFETs are turned off.
In the microcontroller, the 16 bit timer 1 is used to provide a PWM signal for the basic switching cycle. This timer offers number of PWM modes and provides two independent Output Compare ports. These can be used to provide the switching signals for the MOSFETs which include a deadtime. The mode that is most suited to this purpose is Phase Correct PWM mode. In this mode the counter counts up from zero to a value set in a register, then down to zero again. The Output Compare outputs are set and reset as the count passes the values stored in the corresponding Output Compare Registers. By setting these two values to be slightly offset from one another, the duty cycle can be defined along with a deadtime between the two outputs to allow for a period when both MOSFETs are turned on simultaneously. The limitation of this solution is that the deadtime will be the same at the beginning and end of the duty cycle. Certain other microcontrollers (such as the ATTiny461) allow deadtime to be defined directly and differently at each end of the duty cycle.
The program sets the timer clock to full rate and sets a top count value to give the basic PWM cycle period. For an 8MHz clock, a top count of 64 will give a cycle time of 16 microseconds (since the counter counts up then down again), that is a pulse frequency of 62.5kHz that matches the frequency used in the previously described circuits. This results in the PWM having a resolution of 6 bits. The circuit above uses OC1A to drive the high-side MOSFET and must pull high to turn it on. OC1B is used to drive the low-side MOSFET and must also pull high to turn it on. The duty cycle is defined by the high-side MOSFET but the length of this pulse must be limited to allow the MOSFET to turn off before the low-side MOSFET turns on. Therefore the maximum duty cycle is given by the PWM period less the deadtime. The minimum duty cycle is zero, but the low-side MOSFET has a minimum cycle length given by the deadtime.
The A/D input is set to use the provided internal bandgap reference of 1.1V nominal. It can provide 10 bit accuracy if the clock frequency is 200kHz or less. The conversion time is 13 cycles, which is 65 microseconds minimum for this accuracy. If 8 bit accuracy is acceptable, the clock can be increased to 1MHz maximum giving a 13 microsecond conversion time.
A few safety precautions are taken such as to set the watchdog timer to reset the microcontroller in case of non-responsiveness, and to set a brownout detection condition to reset it when the supply voltage drops too low.
In this control algorithm, the output voltage is sampled by the A/D converter using the internal 1.1V bandgap reference voltage. If the measured value is less than 0.55V the PWM duty cycle is set to maximum, otherwise it is set to zero. This is often referred to as hysteretic control, and in fact it does exhibit hysteresis as shown below, although the algorithm doesn't provide it explicitly. This control method is reputed to be unconditionally stable and to have excellent transient response compared to linear control methods. It is very similar to that used in the MC34063. It does have issues with output ripple being somewhat high. Pseudo code for this is:
In the first CRO photograph the bottom trace shows a test port output toggled every time the program goes through its A/D conversion and PWM update loop. The top trace is part of the output ripple.The vertical glitches are due to the PWM switching. The A/D conversion operation and associated processing takes about 18 microseconds (the time scale is 10 microseconds per division). This closely matches the PWM cycle.
The second photograph shows on a longer timescale the ripple at 0.5V per division, and the high-side switch drive signal. There is a delay of about 25 microseconds between the input signal and the A/D conversion, most likely due to the low input bandwidth of the ADC, which is rated at about 40kHz for single ended conversions. This results in the hysteresis that can be observed in the CRO traces. This long delay results in the quite high level of ripple observed. A larger filter capacitor (250µF) reduced the ripple substantially, as expected.
The small kink in the ripple voltage is probably due to minor ripple present on the reference voltage (internal to the microcontroller). With a cleaner reference voltage this kink disappeared.
First created 6 September 2010
Last Modified 13 September 2010
© Ken Sarkies 2010